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Memo Series

093099 Concept for an Affordable High-Data-Rate VLBI Recording and Playback System A. Whitney
002 012401 Interim report on COTS-VLBI Phase I Study A. Whitney
003 030801 Second interim report on COTS-VLBI project A. Whitney
004 071301 The Sustained Disc Streaming Performance of COTS Linux PCs A. Mujunen
005.2 111501 The Sustained Disc Streaming Performance of COTS Linux PCs A. Whitney
006 100201 Using a Mark 5 Prototype at Kokee D.L. Smythe
007.1 122402 The Mark 5A I/O Panel D.L. Smythe
020405 Mark 5A command set A. Whitney J.A. Ball
101001 Mark 5A Input/Output Board Control/Status A. Whitney
012502 Mark 5 Adapter Modules D.L. Smythe
122001 Mark 5A Track Mapping D.L. Smythe
031402 Revised Mark 5 disc-management procedures A.R. Whitney
010402 Mark 5A Operating Modes W. Aldrich
031103 Recently Discovered Model Problems in the Mark 4 Correlator R. Cappallo
031103 Optimally Setting the kdiv Parameter in the Mark 4 Correlator R. Cappallo
010704 VSI Interface Board for the Mark 4 Formatter D. Smythe
062504 Programming the Mark 5A Input-Output Board D. Smythe
111904 Real to real polyphase filter bank A. Rogers H.F.H.
019 112404 Mark 5B design specifications A. Whitney R. Cappallo
020 112904 Simulation of phase cal and low fringe rate phase error using a polyphase filter bank A. Rogers
021 113004 Phase Cal Extraction for the Mark 5B R. Cappallo
022 010305 Mk4 Correlator System Timing R. Cappallo
023.1 041406 Mark 5B status LED's - functions and layout R. Cappallo
024 042706 Mark 5B DIM parameters and procedures A. Whitney W. Aldrich
025 020805 Mark 5B Prototype Test Plan W. Aldrich
026 101705 Mark5B DOM Software Register MAP Rev 1.6 B. Fanous
027 060805 Mark 5B DIM Checking W. Aldrich
028 101705 Windowing and PFB spectral efficiency A. Rogers
029 011706 DBE performance vs number of FIR and interpolator taps A. Rogers
030 013106 Delay Calculations for the Mk5B DOM R. Cappallo
031 120705 MARK 5B I/O BOARD Physical Description W. Aldrich
032 011706 Data Input Module Mark 5B I/O Board Theory of Operation W. Aldrich
033 081706 Zerobaseline test of DBE (Revised) A. Rogers
034.1 051206 Mark 5A Output FPGA Parameters< W. Aldrich
035 042506 Mark 5B Data Output Module (DOM) Hardware Design Document B. Fanous  
036 042706 Mark 5A+ design notes – Revision 3 A. Whitney  
037 042706 Suggested algorithms for Mark 5A+ A. Whitney  
038.2 112009 Hard Disks at High Altitude D.L. Smythe  
039 062106 Mark 5A+ playback modes with Mark 5B recordings A.R. Whitney  
040 071206   Mark 5B Board Schematics A.R. Whitney  
041 120705 Mark 5B Board Component Layout A.R. Whitney  
042 081706 1024/2048 MHz clock synthesizer for DBE A.E.E. Rogers  
043 090506 Simulations of broadband delay measurements A.E.E. Rogers  
044 090506 Some thoughts on the calibration of broadband geodetic VLBI A.E.E. Rogers  
045 091106 5-meter VSI cable at 2048 Mb/s D.L. Smythe  
046 081806 Specifications for enhanced Mark 5 module directory A.R.Whitney et. al.  
047 101006 Timing Offset of the Mark 4 Formatter D.L. Smythe  
048 112006 Cross-talk in dual channel DBE A.E.E. Rogers B. Fanous
049 82410 Updated: Downloading Mark 5B Xilinx code D.L. Smythe  
050 121406 Jumper settings for CIB and Serial Links D.L. Smythe  
051 022707 Measurements of cross-talk and spurious signals levels A.E.E. Rogers  
052 020507 Bench Testing the CIB D.L. Smythe  
053 021607 Changing DMA Mode D.L. Smythe  
054 042507 DOM Station Unit Operation B.Fanous  
055 042507 DOM VSI Operation B. Fanous  
056  101807 Preliminary performance characteristics of Up down converter A.E.E. Rogers  
057  021908 Mark 5C Specification Haystack/NRAO  
058  021908 Mark 5C Data-Frame Specification Haystack/NRAO  
059  110308 Performance characteristics of Updown converter A.E.E. Rogers  
060  111907 Temperature sensitivity of Updown converter A.E.E. Rogers  
061 010708 Mark5C Sotware Interface Specification Haystack/NRAO  
062 010908 Mark5C-, A Proposed Mark5C Emulator Haystack/NRAO  
063.4 081910 Testing the Mark 5B (VSI4) Sampler Module D.L. Smythe  
064.2 042213 Mark 5B(C) DIM Stand-alone testing D.L. Smythe  
065 011508 Proposed phase calibration scheme A.E.E. Rogers  
066 021308 Measurements of cable delay with temperature and flexure A.E.E. Rogers  
067 022608 Dispersion and temperature effects in coax cables A.E.E. Rogers  
068 022608 Measurements of Times Microwave Phase Track II 240 A.E.E. Rogers  
069 111909 Temperature coefficients for LMR-400, LMR-400 ultraflex and LMR-240 (revised) A.E.E. Rogers  
070 022510 Updown converter notes A.E.E. Rogers  
071 041708 Test of Hittite Logic gate A.E.E. Rogers  
072 042208 Simulations of NLTL pulse enhancement A.E.E. Rogers  
073.2 042709

Mark 5B File Utility Programs

D.L. Smythe  
074 061808 Phase calibrator pulse distortion in UDC A.E.E. Rogers  
075 071408 Preliminary circuit for the new phase cal. A.E.E. Rogers  
076 102208 Mark5C Hardware Test and Acceptance Plan C. Ruszczyk  
077 022309 Mark 5 Disk Drive Performance and Reliability D.L. Smythe  
078 021511 Updated: Voltage and Temperature Monitoring on Intel S5000 Boards D.L. Smythe  
079 090605 Updated DBE specifications B. Fanous A.R. Whitney
080 120709 Solid State Drives with Mark 5 D.L. Smythe  
081 121009 Specification for enhanced Mark 5 module directory Note: supersedes memo 046 A.R. Whitney et al.
082 021611 updated: Remote Mark 5 Chassis Power Control D.L. Smythe  
083 122909 Pressurized Disk Drives D.L. Smythe  
084 81110 Revised: Cloning system disks D.L. Smythe  
085 012710 Network Configuration for a Mark 5 D.L. Smythe  
086 020510 Software correlator for station checks A.E.E. Rogers  
087 021610 How to replace a CPU fan (and how not to) D.L. Smythe  
088 032410 Mark 5 Disk Pack Temperature M. Leeuwinga H. Tenkink
089.2 040914 StreamStor Utility Programs D.L. Smythe C.A. Ruszczyk
090.1 060512 Digital Backend Software Command Set - Ver. 1.2 C.A. Ruszczyk M. Taveniku
091.1 052512 Mark 5C Command Set Version 2.0 A.R. Whitney et al.
092 113011 Voltage and Temperature Sensors for Mark 5 Units D.L. Smythe
093 012012 Testing of RDBE PFBG version 1.4.1 S.R. McWhirter
094.1 022813 Conditioning Mark 5 Disk Modules D.L. Smythe
095 030714 How to determine the version of SDK installed on your Mark5 C.A. Ruszczyk
096 030714 Conduant V100 Controller Card SDK 9.2 Upgrade (Mark5A/B) with Debian Etch C.A. Ruszczyk
097 030714 Conduant XF2 Controller Card SDK 9.2 Upgrade (Mark5A/B) with Debian Etch C.A. Ruszczyk
098 030714 Conduant Amazon Controller Card SDK 9.2 Upgrade (Mark5B+) with Debian Etch C.A. Ruszczyk
099 030714 Conduant Amazon Controller Card SDK 9.3a Upgrade (Mark5B+) C.A. Ruszczyk
100 032714 Mark5 User Directory Formats C.A. Ruszczyk B. Eldering H. Verkouter
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