Mark 5 Memo Series

Mark 5 VLBI Data System

The Mark 5 system was developed at Haystack Observatory as the first high-data-rate VLBI data system based on magnetic-disc technology.

Incorporating primarily low-cost PC-based components, the Mark 5 system supports data rates up to 2048 Mbps, recording to an array of 8 inexpensive removable ATA disks.

Support for Mark 5 development was provided by BKG, EVN, KVN, MPI, NASA, NRAO and USNO.

Mark 5 Memos

001Concept for an Affordable High-Data-Rate VLBI Recording and Playback SystemA. Whitney19990930
002Interim report on COTS-VLBI Phase I StudyA. Whitney20010124
003Second interim report on COTS-VLBI projectA. Whitney20010308
004The Sustained Disc Streaming Performance of COTS Linux PCsA. Mujunen20010713
005Preliminary design specifications for Mark 5 VLBI data systemA. Whitney20011115
006Using a Mark 5 Prototype at KokeeD.L. Smythe20011002
007.1The Mark 5A I/O PanelD.L. Smythe20021224
008Mark 5A command setA. Whitney, J.A. Ball20050204
009Mark 5A Input/Output Board Control/StatusA. Whitney20011010
010.1Mark 5 Adapter ModulesD.L. Smythe20020125
011.1Mark 5A Track MappingD.L. Smythe20011220
012.1Revised Mark 5 disc-management proceduresA.R. Whitney20020314
013Mark 5A Operating ModesW. Aldrich20020104
014Recently Discovered Model Problems in the Mark 4 CorrelatorR. Cappallo20030311
015Optimally Setting the kdiv Parameter in the Mark 4 CorrelatorR. Cappallo20030311
016VSI Interface Board for the Mark 4 FormatterD. Smythe20040107
017.1Programming the Mark 5A Input-Output BoardD. Smythe20040625
018Real to real polyphase filter bankA. Rogers, H.F.H.20041119
019Mark 5B design specificationsA. Whitney, R. Cappallo20041124
020Simulation of phase cal and low fringe rate phase error using a polyphase filter bankA. Rogers20041129
021Phase Cal Extraction for the Mark 5BR. Cappallo20041130
022Mk4 Correlator System TimingR. Cappallo20050103
023.1Mark 5B status LED’s – functions and layoutR. Cappallo20060414
024.4Mark 5B DIM parameters and proceduresA. Whitney, W. Aldrich20060427
025Mark 5B Prototype Test PlanW. Aldrich20050208
026Mark5B DOM Software Register MAP Rev 1.6B. Fanous20051017
027Mark 5B DIM CheckingW. Aldrich20050608
028Windowing and PFB spectral efficiencyA. Rogers20051017
029DBE performance vs number of FIR and interpolator tapsA. Rogers20060117
030Delay Calculations for the Mk5B DOMR. Cappallo20060131
031MARK 5B I/O BOARD Physical DescriptionW. Aldrich20051207
032Data Input Module Mark 5B I/O Board Theory of OperationW. Aldrich20060117
033Zerobaseline test of DBE (Revised)A. Rogers20060817
034.1Mark 5A Output FPGA ParametersW. Aldrich20060512
035Mark 5B Data Output Module (DOM) Hardware Design DocumentB. Fanous20060425
036Mark 5A+ design notes – Revision 3A. Whitney20060427
037Suggested algorithms for Mark 5A+A. Whitney20060427
038.2Hard Disks at High AltitudeD.L. Smythe20091120
039Mark 5A+ playback modes with Mark 5B recordingsA.R. Whitney20060621
040Mark 5B Board SchematicsA.R. Whitney20060712
041Mark 5B Board Component LayoutA.R. Whitney20051207
0421024/2048 MHz clock synthesizer for DBEA.E.E. Rogers20060817
043Simulations of broadband delay measurementsA.E.E. Rogers20060905
044Some thoughts on the calibration of broadband geodetic VLBIA.E.E. Rogers20060905
0455-meter VSI cable at 2048 Mb/sD.L. Smythe20060911
046Specifications for enhanced Mark 5 module directoryA.R.Whitney et. al.20060818
047Timing Offset of the Mark 4 FormatterD.L. Smythe20061010
048Cross-talk in dual channel DBEA.E.E. Rogers, B. Fanous20061120
049Updated: Downloading Mark 5B Xilinx codeD.L. Smythe20100824
050Jumper settings for CIB and Serial LinksD.L. Smythe20061214
051Measurements of cross-talk and spurious signals levelsA.E.E. Rogers20070227
052Bench Testing the CIBD.L. Smythe20070205
053Changing DMA ModeD.L. Smythe20070216
054DOM Station Unit OperationB.Fanous20070425
055DOM VSI OperationB. Fanous20070425
056Preliminary performance characteristics of Up down converterA.E.E. Rogers20071018
057Mark 5C SpecificationHaystack/NRAO20080219
058Mark 5C Data-Frame SpecificationHaystack/NRAO20080219
059Performance characteristics of Updown converterA.E.E. Rogers20081103
060Temperature sensitivity of Updown converterA.E.E. Rogers20071119
061Mark5C Sotware Interface SpecificationHaystack/NRAO20080107
062Mark5C-, A Proposed Mark5C EmulatorHaystack/NRAO20080109
063.4Testing the Mark 5B (VSI4) Sampler ModuleD.L. Smythe20100819
064.2Mark 5B(C) DIM Stand-alone testingD.L. Smythe20130422
065Proposed phase calibration schemeA.E.E. Rogers20080115
066Measurements of cable delay with temperature and flexureA.E.E. Rogers20080213
067Dispersion and temperature effects in coax cablesA.E.E. Rogers20080226
068Measurements of Times Microwave Phase Track II 240A.E.E. Rogers20080226
069Temperature coefficients for LMR-400, LMR-400 ultraflex and LMR-240 (revised)A.E.E. Rogers20091119
070Updown converter notesA.E.E. Rogers20100225
071Test of Hittite Logic gateA.E.E. Rogers20080417
072Simulations of NLTL pulse enhancementA.E.E. Rogers20080422
073.2Mark 5B File Utility Programs D.L. Smythe20090427
074Phase calibrator pulse distortion in UDCA.E.E. Rogers20080618
075Preliminary circuit for the new phase cal.A.E.E. Rogers20080714
076Mark5C Hardware Test and Acceptance PlanC. Ruszczyk20081022
077Mark 5 Disk Drive Performance and ReliabilityD.L. Smythe20090223
078Updated: Voltage and Temperature Monitoring on Intel S5000 BoardsD.L. Smythe20110215
079Updated DBE specificationsB. Fanous, A.R. Whitney20050906
080Solid State Drives with Mark 5D.L. Smythe20091207
081Specification for enhanced Mark 5 module directory Note: supersedes memo 046A.R. Whitney et al.20091210
082Remote Mark 5 Chassis Power ControlD.L. Smythe20110216
083Pressurized Disk DrivesD.L. Smythe20091229
084Revised: Cloning system disksD.L. Smythe20100811
085Network Configuration for a Mark 5D.L. Smythe20100127
086Software correlator for station checksA.E.E. Rogers20100205
087How to replace a CPU fan (and how not to)D.L. Smythe20100216
088Mark 5 Disk Pack TemperatureM. Leeuwinga, H. Tenkink20100324
089.2StreamStor Utility ProgramsD.L. Smythe, C.A. Ruszczyk20140409
090.1Digital Backend Software Command Set – Ver. 1.2C.A. Ruszczyk, M. Taveniku20120605
091.1Mark 5C Command Set Version 2.0A.R. Whitney et al.20120525
092Voltage and Temperature Sensors for Mark 5 UnitsD.L. Smythe20111130
093Testing of RDBE PFBG version 1.4.1S.R. McWhirter20120120
094.1Conditioning Mark 5 Disk ModulesD.L. Smythe20130228
095How to determine the version of SDK installed on your Mark5C.A. Ruszczyk20140307
096Conduant V100 Controller Card SDK 9.2 Upgrade (Mark5A/B) with Debian EtchC.A. Ruszczyk20140307
097Conduant XF2 Controller Card SDK 9.2 Upgrade (Mark5A/B) with Debian EtchC.A. Ruszczyk20140307
098Conduant Amazon Controller Card SDK 9.2 Upgrade (Mark5B+) with Debian EtchC.A. Ruszczyk20140307
099Conduant Amazon Controller Card SDK 9.3a Upgrade (Mark5B+)C.A. Ruszczyk20140307
100Mark5 User Directory FormatsC.A. Ruszczyk, B. Eldering, H. Verkouter20140327
101Notes on KOKEE20M phase calB. Corey20181106